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Altima Communications Inc.
AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver GENERAL DESCRIPTION
The AC104QF is a highly integrated, 3.3V, low power, four port, 10Base-T/100Base-TX/FX, Ethernet transceiver implemented in 0.35m CMOS technology. Multiple modes of operation including normal operation, test mode and power saving mode are available through either hardware or software control. Features include MAC interfaces, ENDECs, Scrambler/Descrambler, and Auto-Negotiation (ANeg) with support for parallel detection. The transmitter includes a dual-speed clock synthesizer that only needs one external clock source. The chip has built-in wave shaping driver circuit for both 10Mbps and 100Mbps, eliminating the need for an external hybrid filter. The receiver has an adaptive equalizer / DC restoration circuit for accurate clock / data r ecovery for the 100Base-TX signal. It also provides an on-chip low pass filer / Squelch circuit for the 10Base-T signal. MAC interfaces support four ports of 10/100 RMII. Media Interfaces support 4 ports of 10/100TX or 3 ports 10/100TX and 1 port 100FX.
FEATURES
* * * * 4 RMII * RMII 5Volt tolerant and 2.5Volt capable 4 10/100 TX or 3 10/100 TX and 1 100 FX * Full Duplex or Half Duplex * FEFI on 100FX Very small package * 100PQFP Very low power - TYP < 280mW (/ port) * Cable Detect mode - TYP < 40mW (/ port) * Power Down mo de - TYP < 3.3mW (/ port) * Selectable TX drivers for 1:1 or 1.25:1 transformers for additional power reduction 3.3Volt .35micron CMOS Fully compliant with * IEEE 802.3 / 802.3u * RMII * UNH test labs Baseline Wander Compensation Multi-Function LED outputs Cable length indicator Reverse polarity detection and correction with Register Bit indication - Automatic or Forced 8 programmable interrupts Diagnostic registers
* *
* * * * * *
BLOCK DIAGRAM
Port 0 Port 1 Port 2 Port 3
PCS .Framer .Carrier Detect .4B/5B PMA .Clock Recov. .Link Monitor .Signal Detect TP_PMD 100TX .MLT-3 .BLW .Stream Cipher
100RX RMII/MII
TXOP/N(0) RXIP/N(0) TXOP/N(1) RXIP/N(1) TXOP/N(2) RXIP/N(2) TXOP/N(3)
25 MHz 10TX
Mux
RXIP/N(3)
Interface
10BASE-T
10RX
FXTP/N(3) FXRP/N(3)
MII SMI
Control/Status
20 MHz
RX
FLP
MII Serial Management Interface and Registers
PLL Clk Gen. Test/LED Control
25 MHz
AutoNegotiation
PHYAD[4:0]
XTLP/N CKIN TEST[3:0] LED Drivers
AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
REVISION HISTORY REVISION# DATE 1.0 July 1998 3.2 June 2000 4.0 Sept 12, 2000 CHANGE BY xx xx Helene CHANGE DESCRIPTION Preliminary Release Final Release 1. Change the default value of register 3 [15:0] = 101010101000001 on page 20 2. Enhance the descriptions of the DPLX and SPEED (register 18.11 and 18.10) on page 24
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
General Description......................................................................................................................................................................... 1 Features.............................................................................................................................................................................................. 1 Block Diagram................................................................................................................................................................................. 1 Pin Diagram - AC104QF................................................................................................................................................................ 5 Pin Descriptions............................................................................................................................................................................... 6 MDI (Media Dependent Interface) Pins.....................................................................................................................................6 RMII (Reduced Media Independent Interface) Pins................................................................................................................7 SMI (Serial Management Interface) Pins ..................................................................................................................................7 Phy Address Pins...........................................................................................................................................................................8 Mode Pins........................................................................................................................................................................................8 LED Pins .........................................................................................................................................................................................8 Power and Ground Pins ................................................................................................................................................................9 Functional Description.................................................................................................................................................................. 10 MAC Interface................................................................................................................................................................................ 10 RMII ...................................................................................................................................................................................................10 SMI ...............................................................................................................................................................................................10 Interrupt.........................................................................................................................................................................................11 Carrier Sense / RX_DV ..............................................................................................................................................................11 Media Interface .............................................................................................................................................................................. 11 10Base-T ...........................................................................................................................................................................................11 Transmit Function........................................................................................................................................................................11 Receive Function .........................................................................................................................................................................11 Link Monitor.................................................................................................................................................................................11 100Base-TX ......................................................................................................................................................................................11 Transmit Function........................................................................................................................................................................11 Parallel to Serial, NRZ to NRZI, and MLT3 Conversion....................................................................................................12 Receive Function .........................................................................................................................................................................12 Baseline Wander Compensation...............................................................................................................................................12 Clock/Data Recovery ..................................................................................................................................................................12 Decoder/De-scrambler ................................................................................................................................................................13 Link Monitor.................................................................................................................................................................................13 100Base-FX......................................................................................................................................................................................13 Transmit Function........................................................................................................................................................................13 Receive Function .........................................................................................................................................................................13 Link Monitor.................................................................................................................................................................................13 Far-End-Fault-Indication (FEFI)...............................................................................................................................................13 10Base-T/100Base-TF/FX .............................................................................................................................................................14 Multi-Mode Transmit Driver.....................................................................................................................................................14 Adaptive Equalizer ......................................................................................................................................................................14 PLL Clock Synthesizer ...............................................................................................................................................................14 Jabber and SQE (Heartbeat).......................................................................................................................................................14 Reverse Polarity Detection and Correction .............................................................................................................................14 Initialization and Setup................................................................................................................................................................. 15 Hardware Configuration................................................................................................................................................................15 Software Configuration ..................................................................................................................................................................15 LEDs ..............................................................................................................................................................................................15 Auto-Negotiation.............................................................................................................................................................................15 Parallel Detection...........................................................................................................................................................................16 Diagnostics.......................................................................................................................................................................................16 Loopback Operation....................................................................................................................................................................16 Cable Length Indicator...............................................................................................................................................................16 Reset and Power............................................................................................................................................................................. 16 Clock................................................................................................................................................................................................ 17 Register Descriptions.................................................................................................................................................................... 18 2055 Gateway Parkway Suite 700, San Jose, CA 95110 (408) 453-3700 (www.altimacom.com) Altima Communications Inc. reserves the right to make changes to this document without notice. Document Revision 4.0 Page 3 of 37
AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
Registers 1-7.....................................................................................................................................................................................18 Registers 8-31...................................................................................................................................................................................18 Register 0: Control Register.......................................................................................................................................................19 Register 1: Status Register.........................................................................................................................................................20 Register 2: PHY Identifier 1 Register......................................................................................................................................20 Register 3: PHY Identifier 2 Register......................................................................................................................................20 Register 4: Auto-Negotiation Advertisement Register..........................................................................................................21 Register 5: Auto-Negotiation Link Partner Ability Register/Link Partner Next Page Message....................................21 Register 6: Auto-Negotiation Expansion Register.................................................................................................................22 Register 7: Auto-Negotiation Next Page Transmit Register................................................................................................22 Register 16: BT and Interrupt Level Control Register..........................................................................................................23 Register 17: Interrupt Control/Status Register........................................................................................................................23 Register 18: Diagnostic Register...............................................................................................................................................24 Register 19: Power/Loopback Register....................................................................................................................................24 Register 20: Cable measurement capability Register............................................................................................................24 Register 21: Receive Error Counter..........................................................................................................................................24 Register 24: Mode Control Register.........................................................................................................................................25 Mode Table ...................................................................................................................................................................................25 4B/5B Code-Group Table ............................................................................................................................................................ 26 SMI Read/Write Sequence........................................................................................................................................................... 27 LED Configurations...................................................................................................................................................................... 27 ELECTRICAL CHARACTERISTICS ...................................................................................................................................... 27 ELECTRICAL CHARACTERISTICS ...................................................................................................................................... 28 Absolute Maximum Ratings...........................................................................................................................................................28 Operating Range..............................................................................................................................................................................28 Total Power Consumption..........................................................................................................................................................28 TTL I/O Characteristics ..............................................................................................................................................................28 REFCLK and XTAL Pins ..........................................................................................................................................................28 I/O Characteristics - LED/CFG Pins .......................................................................................................................................29 100 BASE-TX Transceiver Characteristics ............................................................................................................................29 10 BASE-T Transceiver Characteristics..................................................................................................................................29 100 BASE-FX Transceiver Characteristics.............................................................................................................................30 10 BASE-T Link Integrity Timing Characteristics................................................................................................................30 Digital Timing Characteristics .....................................................................................................................................................31 Power on Reset.............................................................................................................................................................................31 Management Data Interface .......................................................................................................................................................31 100Base-TX/FX & 10Base-T RMII Transmit System Timing ...........................................................................................32 100Base-TX/FX & 10Base-T RMII Receive System Timing .............................................................................................33 TX Application Termination ..........................................................................................................................................................34 FX Application Termination..........................................................................................................................................................35 Power and ground filtering for AC104QF..................................................................................................................................36 Package dimensions for AC104QF (100 pin PQFP) ................................................................................................................37
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver PIN DIAGRAM - AC104QF
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
OVDD RXD[0](0) RXD[1](0) CVDD TX_EN(1) TXD[0](1) TXD[1](1) OGND OGND CRS_DV(1) RX_ER(1) RXD[0](1) RXD[1](1) CVDD REF_CLK MDC MDIO TX_EX(2) OVDD TXD[0](2) TXD[1](2) CGND CRS_DV(2) RX)ER(2) RXD[0](2) RXD[1](2) CVDD TX_EX(3) OGND TXD[0](3)
RX_ER(0) CRS_DV(0) CGND TXD[1](0) TXD[0](0) TX_EN(0) OGND LEDDPX(1) / PHYAD[4] LEDACT(1) / PHYAD[3] LEDSPD(1) / PHYAD[2] LEDDPX(0) / FX_DIS LEDACT(0) LEDSPD(0) / TP125 INTR RST* GAGND IBREF GAVDD GAVDD AVDD
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
AC104QF
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
TXD[1](3) CGND CRS_DV(3) RX_ER(3) / PHYAD_ST RXD[0](3) RXD[1](3) OVDD LEDSPD(2) / FORCE100 LEDACT(2) LEDDPX(2) LEDSPD(3) / BURN_IN* LEDACT(3) / ANEGA LEDDPX(3) / SCRAM_EN FXTN(3) FXTP(3) FXRN(3) / TST[3] FXRP(3) / TST[2] SDN(3) / TST[1] SDP(3) / TST[0] AVDD
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RXIN(0) RXIP(0) AGND AGND TXOP(0) TXON(0) AVDD AVDD TXON(1) TXOP(1) AGND AGND RXIP(1) RXIN(1) AVCC AVCC RXIN(2) RXIP(2) AGND AGND TXOP(2) TXON(2) AVDD AVDD TXON(3) TXOP(3) AGND AGN RXIP(3) RXIN(3)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver PIN DESCRIPTIONS
Many of the pins of these devices have multiple functions. The multi-function pins will be designated by bolding of the pin number. Separate descriptions of these pins will be listed in the proper sections. Designers must assure that they have identified all modes of operation prior to final design.
NOTES: The pin assignment shown below and in the pin description table is subject to change without notice. The user is advised to contact Altima Communications Inc. before implementing any design based on the information provided in this data sheet. Signals types: I = input O = output Z = high impedance U = internally pull up D = internally pull down A = analog signal * = Active Low Signal NC = No Connect pin MDI (Media Dependent Interface) Pins Pin Name RXIN(0) RXIN(1) RXIN(2) RXIN(3) RXIP(0) RXIP(1) RXIP(2) RXIP(3) TXON(0) TXON(1) TXON(2) TXON(3) TXOP(0) TXOP(1) TXOP(2) TXOP(3) FXRP(3) FXRN(3) FXTP(3) FXTN(3) SDP(3) SDN(3) Pin # 1 14 17 30 2 13 18 29 6 9 22 25 5 10 21 26 34 35 36 37 32 33 Type AI AI AI AI AI AI AI AI AO AO AO AO AO AO AO AO AI/O AI/O AO AO A/I,O A/I,O Description Receiver input Negative for both 10Base-T and 100Base-TX.
Receiver input Positive for both 10Base-T and 100Base-TX.
Transmitter output Negative for both 10Base-T and 100Base-TX.
Transmitter output Positive for both 10Base-T and 100Base-TX.
Receiver input Positive for 100Base-FX. (Port-3) Receiver input Negative for 100Base-FX. (Port-3) Transmitter output Positive for 100Base-FX. (Port-3) Transmitter output Negative for 100Base-FX. (Port-3) Signal Detect Input (For port 3 only). Indicates signal quality status on the fiberoptic link in 100Base-FX mode. When the signal quality is good, the SDP pin should be driven high relative to the SDN pin.
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
RMII (Reduced Media Independent Interface) Pins Pin Name TXD[1:0](0) TXD[1:0](1) TXD[1:0](2) TXD[1:0](3) TX_EN(0) TX_EN(1) TX_EN(2) TX_EN(3) RXD[1:0](0) RXD[1:0](1) RXD[1:0](2) RXD[1:0](3) CRS_DV(0) CRS_DV(1) CRS_DV(2) CRS_DV(3) RX_ER(0) RX_ER(1) RX_ER(2) RX_ER(3) REFCLK Pin # 84, 85 74, 75 60, 61 50, 51 86 76 63 53 78,79 68,69 55,56 45,46 82 71 58 48 81 70 57 47 66 Type I/O, D I/O, D I/O, D I/O, D I/O,D I/O,D I/O,D I/O,D I/O, D I/O, D I/O, D I/O, D I/O, D I/O, D I/O, D I/O, D I/O, D O O I/O, D I Description RMII Transmit Data. The MAC will source TXD[1:0](n) synchronous with REFCLK when TX_EN(n) is asserted.
RMII Transmit Enable. TX_EN(n) is asserted high by the MAC to indicate that valid data for transmission is presented on the TXD[1:0](n).
RMII Receive Data. The Phy will source RXD[1:0](n) synchronous with REFCLK when CRS_DV(n) is asserted.
CRS_DV(n) is asserted high when media is non-idle.
RMII Receive Error. When RX_ER is asserted high, it indicates an error has been detected during frame reception.
Reference Clock Input - 50 MHz-100PPM TTL
SMI (Serial Management Interface) Pins Pin Name MDIO MDC INTR Pin # 64 65 94 Type I/O, D I, D Z Description Management Data Input/Output. Bi-directional data interface. 1.5K pull up resistor required (as specified in IEEE-802.3). Management Data Clock. 0 to 25 MHz clock sourced by the MAC for transfer of MDIO data. Interrupt. See Registers 16 and 17 for polarity and sources. The INTR pin has a high impedance output, a 1K pull-up or pull-down resistor is needed.
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
Phy Address Pins Pin Name PHYAD_ST PHYAD [4] PHYAD [3] PHYAD [2] Pin # 47 88 89 90 Type I/O,D I/O I/O I/O Description 1 at reset = 0-XXX00, 1-XXX01, 2-XXX10, 3-XXX11 0 at reset = 0-XXX01, 1-XXX10, 2-XXX11, 3-XXX00 PHY Address [4:2]. These pins set the three MSB's for SMI PHY address. PHYAD [1:0] are internally wired to four ports. (See PHYAD_ST) The PHYAD will also determine the scramble seed, this will help to reduce EMI when there are multiple ports switching at the same time.
Mode Pins Pin Name FX_DIS TP125 FORCE100 Pin # 91 93 43 Type I/O I/O I/O Description FX Disable. Pulled low upon reset will put port 3 in 100FX mode. Transformer Ratio. Pulled low upon reset will select transmit transformer ratio to be 1.25:1. Pulled high is 1:1 transformer. FORCE100: Force 100Base-X Operation. When this signal is pulled high and ANENGA is low upon reset, all ports will be forced to 100Base-TX operation. When asserted low and ANENGA is low, all ports are forced to 10Base-T operation. When ANENGA is high, FORCE100 has no effect on operation. Scrambler Enable. Pulled low upon reset will bypass the scrambler. Pulled high is scrambler enabled. Auto-Negotiation Ability. Asserted high means auto-negotiation enable while low means manual selection through FDXEN, F100. Burn-In mode. Burn-in mode for reliability assurance control. This is reserved for internal testing only.
SCRAM_EN ANEGA BURN_IN*
38 39 40
I/O I/O I/O
LED Pins Pin Name LEDDPX[0] LEDDPX[1] LEDDPX[2] LEDDPX[3] LEDACT_LNK[0] LEDACT_LNK[1] LEDACT_LNK[2] LEDACT_LNK[3] LEDSPD[0] LEDSPD[1] LEDSPD[2] LEDSPD[3] Pin # Type Description
91 I/O,U Port[n] Duplex LED. Active state indicates Full Duplex or Collision in Half 88 I/O,U Duplex mode. 41 I/O,U 38 I/O,U 92 I/O,U Port[n] Activity/Link LED. Active state indicates a valid link. When there is 89 I/O,U receive or transmit activity, LED will toggle between high and low for 30 ms 42 I/O,U interval. 39 I/O,U 93 I/O,U Port[n] Speed LED. Active state indicates 100Base-TX mode. 90 I/O,U 43 I/O,U 40 I/O,U Polarity of LEDs is determined by polarity of mode pins. See LED example
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
Miscellaneous Pins Pin Name RST* Pin # 95 Type I, U Description Reset. An active low input will force a known initialization state. The reset pulse duration must be > 100 us. Setting MII Reg. 0.15 will assert software reset, which has the same functionality as the hardware reset. Reference Bias Resistor. Must be tied to analog ground through an external 10K (1%) resistor. Test. Outputs during test mode.
IBREF TST[0] TST[1] TST[2] TST[3]
97 32 33 34 35
A A/I,O
Power and Ground Pins Pin Name OVDD OGND CVDD CGND AVDD Pin # 44, 62, 80 52, 72, 87 54, 67, 77 49, 59, 73, 83 7, 8, 15, 16, 23, 24, 31, 100 3, 4, 11, 12, 19, 20, 27, 28 98,99 96 Type P G P G P Digital +3.3V power supply for I/O. Digital ground for I/O. Digital +3.3V power supply for Core logic. Digital ground for Core logic. +3.3V power supply for Analog circuit. Description
AGND
G
Ground for Analog circuit.
GAVDD GAGND
P G
+3.3V power supply for common analog circuits. Ground for common analog circuits.
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver FUNCTIONAL DESCRIPTION
The AC104QF physical layer device (Phy) integrates the 100Base-X and 10Base-T functions in a single four port chip that is used in Fast Ethernet 10/100 Mbps applications. The 100Base-X section consists of PCS, PMA, and PMD functions, and the 10Base-T section consists of Manchester ENDEC and transceiver functions. The device performs the following functions: * * * * * * * * * * * * * 4B/5B MLT3 NRZI Manchester Encoding and Decoding Clock and Data Recovery Stream Cipher Scrambling / De-Scramb ling Adaptive Equalization Line Transmission Carrier Sense Link Integrity Monitor Auto-Negotiation (ANeg) RMII MAC connectivity MII Management Function Phy when there is valid data on the transmit bus. In 100M mode the Phy will read 2 bits from TXD[1:0] for each cycle of REFCLK. In 10M mode the Phy will read 2 bits of data from TXD[1:0] every 10th cycle of REFCLK. The Serial Management Interface (SMI) is shared between all ports in the Phy. This totals 7 pins per port plus 3 per Phy, whereas MII has 18 pins per port.
SMI
The Phy's internal registers are accessible only through the MII 2-wire Serial Management Interface (SMI). MDC is a clock input to the Phy which is used to latch in or out data and instructions for the Phy. The clock can run at any speed from DC to 25 MHz. MDIO is a bi-directional connection used to write instructions to, write data to, or read data from the Phy. Each data bit is latched either in or out on the rising edge of MDC. MDC is not required to maintain any speed or duty cycle, provided no half cycle is less than 20ns and that data is presented synchronous to MDC. MDC/MDIO are a common signal pair to all ports on a design. Therefore, each port needs to have its own unique Physical Address. The Physical Address of the Phy is set using the pins defined as PHYAD[4:2]. These input signals are strapped externally and sampled as reset is negated. PHYAD[1:0] are addressed for each port internal to the Phy. Internal addresses are either 00, 01, 10, 11 or 01, 10, 11, 00 depending on the polarity of PHYAD_ST during reset. At idle, the PHY is responsible to pull MDIO line to a high state. Therefore, a 1.5K Ohms resistor is required to connect MDIO line to Vcc. The PHYAD can be reprogrammed via software. A detailed definition of the Serial Management registers follows.
It also provides an RMII consortium compatible Reduced Media Independent Interface (RMII) to communicate with an Ethernet Media Access Controller (MAC). Selection of 10 or 100 Mbps operation is based on the settings of internal Serial Management Interface registers or determined by the on-chip ANeg logic. The device can operate in 10 or 100 Mbps with full duplex or half-duplex mode on a per port basis. Port 3 can also be configured for 100Base-FX.
MAC INTERFACE
RMII
The Reduced Media Independent Interface (RMII) is used to connect the Phy with the MAC. The PHY At the beginning of a read or write cycle, the MAC and MAC obtain their clock from a common 50 MHz will send a continuous 32 bits of one at the MDC source, such as a clock oscillator. This clock is clock rate to indicate preamble. A zero and a one shared by all ports within the Phy for transmitting will follow to indicate start of frame. A read OP and receiving data on 2 individual 2-bit data buses. code is a one and a zero, while a write OP code is a CRS and RXDV are muxed together to indicate to the zero and a one. These will be followed by 5 bits to MAC when there is valid data on the receive bus. In indicate PHY address and 5 bits to indicate register 100M mode RXD[1:0] is sampled on every cycle of address. Then 2 bits follow to allow for turn around REFCLK. In 10M mode RXD[1:0] is sampled on time. For read operation, the first bit will be high th every 10 cycle of REFCLK. RXER is generated by impedance. Neither the PHY nor the station will the Phy to indicate a receive error to the MAC. assert this bit. During the second bit time, the PHY TX_EN is generated by the MAC to indicate to the 2055 Gateway Parkway Suite 700, San Jose, CA 95110 (408) 453-3700 (www.altimacom.com) Altima Communications Inc. reserves the right to make changes to this document without notice. Document Revision 3.2 Page 10 of 37
AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
will assert this bit to a zero. For write operation, the station will drive a one for the first bit time, and a zero for the second bit time. The 16 bits data field is then presented. The first bit that is transmitted is bit 15 of the register content. (See SMI Read/Write Sequence) Interrupt The INTR pin on the Phy will be asserted whenever one of 8 selectable interrupt events occur. Assertion state is programmable to either high or low through the INTR_LEVL register bit. Selection is made by setting the appropriate bit in the upper half of the Interrupt Control / Status register. When the INTR bit goes active, the MAC interface is required to read the Interrupt Control / Status register to determine which event caused the interrupt. The Status bits are read only and clear on read. When INTR is not asserted, the pin is held in a high impedance state. Carrier Sense / RX_DV Carrier sense is asserted asynchronously on the CRS pins as soon as activity is detected on the receive data stream. RX_DV is asserted as soon as a valid SSD (Start-of-Stream Delimiter) is detected. Carrier sense and RX_DV are de-asserted synchronously upon detection of a valid end of stream delimiter or two consecutive idle code groups in the receive data stream. However, if the carrier sense is asserted and a valid SSD is not detected immediately, RX_ER is asserted instead of RX_DV. In 10Base-T mode, CRS is asserted asynchronously when the valid preamble and data activity is detected on the RXIP and RXIN pins. In the half duplex mode, the CRS is activated during the transmit and receiving of data. In the full duplex mode, the CRS is activated during data reception only. Transmit Function Parallel to Serial logic is used to convert the 2 -bit (RMII) or 4-bit (MII) data into the serial stream. The serialized data goes directly to the Manchester encoder where it is synthesized through the output waveshaping driver. The waveshaper reduces any EMI emission by filtering out the harmonics, therefore eliminating the need for an external filter. Receive Function The received signal passes through a low-pass filter, which filters out the noise from the cable, board, and transformer. This eliminates the need for a 10Base-T external filter. A Manchester decoder converts the incoming serial stream. Serial to Parallel logic is used to generate the 2-bit (RMII) or 4-bit (MII) data. Link Monitor The 10-Base-T link-pulse detection circuit will constantly monitor the RXIP/RXIN pins for the presence of valid link pulses. In the absence of valid link pules, the Link Status bit will be cleared and the Link LED will de-assert.
100BASE-TX
When configured to run in 100Base-TX mode, either through hardware configuration, software configuration or ANeg, the Phy will support all the features and parameters of the industry standards. Transmit Function In 100Base-TX mode, the Phy transmit function converts synchronous 2-bit (RMII) or 4-bit (MII) data to a pair of 125 Mbps differential serial data streams. The serial data is transmitted over network twisted pair cables via an isolation transformer. Data conversion includes 4B/5B encoding, scrambling, parallel to serial, NRZ to NRZI, and MLT-3 encoding. The entire operation is synchronous to 25 MHz and 125 MHz clock. Both clocks are generated by an on-chip PLL clock synthesizer that is locked on to an external 25 MHz clock source. The transmit data is transmitted from the MAC to the Phy via the TXD[n:0] signals. The 4B/5B encoder replaces the first two nibbles of the preamble from the MAC frame with a /J/K/ code-group pair Start-ofStream Delimiter (SSD), following the onset of TX_EN signal. The 4B/5B encoder appends a /T/R/ code-group pair End-of-Stream Delimiter (ESD) to the end of transmission in place of the first two IDLE
MEDIA INTERFACE
10BASE-T
When configured to run in 10Base-T mode, either through hardware configuration, software configuration or ANeg, the Phy will support all the features and parameters of the industry standards.
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
code-groups that follow the negation of the TX_EN signal. The encapsulated data stream is converted from 4 -bit nibbles to 5-bit code-groups. During the inter-packet gap, when there is no data present, a continuous stream of IDLE code-groups are transmitted. When TX_ER is asserted while TX_EN is active, the Transmit Error code-group /H/ is substituted for the translated 5B code word. The 4B/5B encoding is bypassed when Reg. 21.1 is set to "1", or the PCSBP pin is strapped high. In 100Base-TX mode, the 5-bit transmit data stream is scrambled as defined by the TP-PMD Stream Cipher function in order to reduce radiated emissions on the twis ted pair cable. The scrambler encodes a plain text NRZ bit stream using a key stream periodic sequence of 2047 bits generated by the recursive linear function: X[n] = X[n-11] + X[n-9] (modulo 2) The scrambler reduces peak emissions by randomly spreading the signal energy over the transmitted frequency range, thus eliminating peaks at any single frequency. For repeater applications, where all ports transmit the same data simultaneously, signal energy is spread further by using a non-repeating sequence for each Phy, i.e., the scrambled seed is unique for each different Phy based on the Phy address. When Dis_Scrm is set to "0" the data scrambling function is disabled, the 5-bit data stream is clocked directly to the device's PMA sublayer. Parallel to Serial, NRZ to NRZI, and MLT3 Conversion The 5-bit NRZ data is clocked into Phy's shift register with a 25 MHz clock, and clocked out with a 125 MHz clock to convert it into a serial bit stream. The serial data is converted from NRZ to NRZI format, which produces a transition on Logic 1 and no transition on Logic 0. To further reduce EMI emissions, the NRZI data is converted to an MLT-3 signal. The conversion offers a 3dB to 6dB reduction in EMI emissions. This allows system designers to meet the FCC Class B imit. Whenever there is a l transition occurring in NRZI data, there is a corresponding transition occurring in the MLT-3 data. For NRZI data, it changes the count up/down direction after every single transition. For MLT-3 data, it changes the count up/down direction after every two transitions. The NRZI to MLT-3 data conversion is implemented without reference to the bit timing or clock information. The conversion requires detecting the transitions of the incoming NRZI data and setting the count up/down direction for the MLT-3 data. Asserting FX_SEL high will disable this encoding. The slew rate of the transmitted MLT-3 signal can be controlled to reduce EMI emissions. The MLT-3 signal after the magnetic has a typical rise/fall time of approximately 4 ns, which is within the target range specified in the ANSI TP- PMD standard. This is guaranteed with either 1:1 or 1.25:1 transformer. Receive Function The 100Base-TX receive path functions as the inverse of the transmit path. The receive path includes a receiver with adaptive equalization and DC restoration in the front end. It also includes a MLT-3 to NRZI converter, 125 MHz data and clock recovery, NRZI/NRZ conversion, Serial-to-Parallel conversion, de-scrambler, and 5B/4B decoder. The receiver circuit starts with a DC bias for the differential RX+/- inputs, followed with a low-pass filter to filter out high frequency noise from the transmission channel media. An energy detect circuit is also added to determine whether there is any signal energy on the media. This is useful in the powersaving mode. The amplification ratio and slicer's threshold is set by the on-chip bandgap reference. Baseline Wander Compensation The 100Base-TX data stream is not always DC balanced. The transformer blocks the DC components of the incoming signal, thus the DC offset of the differential receive inputs can drift. The shifting of the signal level, coupled with non-zero rise and fall times of the serial stream can cause pulse-width distortion. This creates jitter and possible increase in the bit error rates. Therefore, a DC restoration circuit is needed to compensate for the attenuation of the DC component. This Phy implements a patent-pending DC restoration circuit. Unlike the traditional implementation, the circuit does not need the feedback information from the slicer or the clock recovery circuit. This design simplifies the circuit design and eliminates any random/systematic offset on the receive path. In the 10BaseT and the 100BaseFX modes, the baseline wander correction circuit is not required, and therefore is disabled. Clock/Data Recovery The equalized MLT-3 signal passes through the slicer circuit, and gets converted to NRZI format. The Phy uses a proprietary mixed-signal phase locked loop (PLL) to extract clock information from the incoming NRZI data. The extracted clock is used to re-time the
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
data stream and set the data boundaries. The transmit clock is locked to the 50 MHz clock input (RMII) or 25 MHz clock input (MII) while the receive clock is locked to the incoming data streams. When initial lock is achieved, the PLL switches to the data stream, extracts the 125 MHz clock, and uses it for the bit framing for the recovered data. The recovered 125 MHz clock is also used to generate the 25 MHz MII_RXC (MII). The PLL requires no external components for its operation and has high noise immunity and low jitter. It provides fast phase alignment and locks to data in one transition. Its data/clock acquisition time after power-on is less than 60 transitions. The PLL can maintain lock on runlengths of up to 60 data bits in the absence of signal transitions. When no valid data is present, i.e. when the SD is de-asserted, the PLL will switch and lock on to REFCLK. This provides a continuously running MII_RXC (MII). At the PCS interface, the 5 bit data RXD[4:0] is synchronized to the 25 MHz RX_CLK. Decoder/De-scrambler The de-scrambler detects the state of the transmit Linear Feedback Shift Register (LFSR) by looking for a sequence representing consecutive idle codes. The de-scrambler acquires lock on the data stream by recognizing IDLE bursts of 30 or more bits and locks its frequency to its de-ciphering LFSR. Once lock is acquired, the device can operate with an inter-packet-gap (IPG) as low as 40 nS. However, before lock is acquired, the de-scrambler needs a minimum of 270 nS of consecutive idles in between packets in order to acquire lock. The de-ciphering logic also tracks the number of consecutive errors received while the RX_DV is asserted. Once the error counter exceeds its limit currently set to 64 consecutive errors, the logic assumes that the lock has been lost, and the de-cipher circuit resets itself. The process of regaining lock will start again. Stream cipher de-scrambler is not used in the 100Base-FX and the 10Base-T modes. Link Monitor Signal level is detected through a squelch detection circuitry. A signal detect (SD) circuit allows the equalizer to assert high whenever the peak detector detects a post-equalized signal with peak to ground voltage greater than 400 mV. This is approximately 40% of a normal signal voltage level. In addition, the energy level must be sustained for longer than 2~3 S in order for the signal detect signal to stay on. The SD gets de-asserted approximately 1~2 s after the energy level drops consistently below 300 mV from peak to ground. The link signal is forced low during a local loopback operation (Loopback register bit is set) and forced to high when a remote loopback is taking place (EN_RPBK is set). In forced 100Base-TX mode, when a cable is unplugged or no valid signal is detected on the receive pair, the link monitor enters in the "link fail" state and NLP's are transmitted. When a valid signal is detected for a minimum period of time, the link monitor enters Link Pass State and transmits MLT-3 signal.
100BASE-FX
When port 3 is configured to run in 100Base-FX mode, either through hardware configuration or software configuration (100Base-FX does not support ANeg) the Phy will support all the features and parameters of the industry standards. Transmit Function The serialized data bypasses the scrambler and 4B/5B encoder in FX mode. The output data is NRZI PECL signals. The PECL level signals are used to drive the Fiber-transmitter. Receive Function In 100Base-FX mode, signal is received through the PECL receiver inputs, and directly passed to the clock recovery circuit for data/clock extraction. In FX mode, the scrambler/de-scrambler cipher function is bypassed. Link Monitor In 100Base-FX mode, the external fiber-optic receiver performs the signal energy detection function and communicates this information directly to the Phy's SDP pin. Far-End-Fault-Indication (FEFI) ANeg provides the mechanism to inform the link partner that a remote fault has occurred. However, ANeg is disabled in the 100Base-FX applications. An alternative in-band signaling function (FEFI) is used to signal a remote fault condition. FEFI is a stream of 84 consecutive ones followed by one logic zero. This
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
pattern is repeated 3 times. A FEFI will signal under 3 conditions: 1) When no activity is received from the link partner, 2) When the clock recovery circuit detects a signal error or PLL lock error, 3) When management entity sets the transmit Far-End-Fault bit. The FEFI mechanism is enabled by default in the 100Base-FX mode, and is disabled in 100Base-TX or 10Base-T modes. The register setting can be changed by software after reset. meter cable is 21 dB. The worst case cable attenuation is around 24-26 dB as defined by TPPMD specification. The amplitude and phase distortion from the cable cause inter-symbol interference (ISI) which makes clock and data recovery difficult. The adaptive equalizer s designed to closely match the inverse i transfer function of the twisted-pair cable. The equalizer has the ability to changes its equalizer frequency response according to the cable length. The equalizer will tune itself automatically for any cable, compensating for the amplitude and phase distortion introduced by the cable. PLL Clock Synthesizer The Phy includes an on-chip PLL clock synthesizer that generate 25 MHz and 125 MHz clocks for the 100Base-TX circuitry. It also generates 20 MHz and 100 MHz clocks for the 10BaseT and ANeg circuitry. The PLL clock generator uses a fully differential VCO cell that introduces very low jitter. The Zero Dead Zone Phase Detection method implemented in the Phy design provides excellent phase tracking. A charge pump with charge sharing compensation is also included to further reduce jitter at different loop filter voltages. The on-chip loop filter eliminates the need for external components and minimizes the external noise sensitivity. Only one external 50 MHz (RMII) or 2 MHz (MII) crystal or clock source is 5 required as a reference clock. After power-on or reset, the PLL clock synthesizer generates the 20 MHz clock output until the 100Base-X operation mode is selected. Jabber and SQE (Heartbeat) After the MAC transmitter exceeds the jabber timer (46mS), the transmit and loopback functions will be disabled and COL signal get asserted. After TX_EN goes low for more than 500 ms, the TP transmitter will reactivate and COL gets de-asserted. Setting Jabber Disable will disable the jabber function. When the SQE test is enabled, a COL pulse with 515BT is asserted after each transmitted packet. SQE is enabled in 10Base-T by default, and can be disabled via SQE Test Inhibit. Reverse Polarity Detection and Correction
10BASE-T/100BASE-TF/FX
Multi-Mode Transmit Driver The multi-mode driver transmits the MLT-3 coded signal in 100Base-TX mode, NRZI coded signal in 100Base-FX mode, and Manchester coded signal in 10Base-T mode. In 100Base-FX mode, no filtering is performed. The transmit driver utilizes a current drive output which is well balanced and produces a low noise PECL signal. PECL voltage levels are produced with resistive terminations. In 10BaseT mode, high frequency pre-emphasis is performed to extend the cable-driving distance without the external filter. The FLP and NLP pulses are also drive out through the 10BaseT driver. The 10BaseT and 100BaseTX transmit signals are multiplexed to the transmit output driver. This arrangement results in using the same external transformer for both the 10BaseT and the 100BaseTX. The driver output level is set by a builtin bandgap reference and an external resistor connected to the IBREF pin. The resistor sets the output current for all modes of operation. The TXOP/N outputs are open drain devices with a serial source to I/O pad resistance of 10 max. When the 1:1 transformer is used, the current rating is 40 mA for the 2Vp-p MLT-3 signal, and 100 mA for the 5Vp-p Manchester signal. One can use a 1.25:1 transmit transformer for a 20% output driver power reduction. This will decrease the drive current to 32 mA for 100Base-TX operation, and 80 mA for 10Base-T operation. Adaptive Equalizer The Phy is designed to accommodate a maximum of 150 meters UTP CAT-5 cable. An AT&T 1061 CAT5 cable of this length typically has an attenuation of 31 dB at 100 MHz. A typical attenuation of 100-
Certain cable plants have crossed wiring on the twisted pairs; the reversal of TXIN and TXIP. Under normal circumstances this would cause the receive circuitry to reject all data. When the Auto Polarity 2055 Gateway Parkway Suite 700, San Jose, CA 95110 (408) 453-3700 (www.altimacom.com) Altima Communications Inc. reserves the right to make changes to this document without notice. Document Revision 4.0 Page 14 of 37
AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
Disable bit is cleared, the Phy has the ability to detect the fact that either 8 NLPs or a burst of FLPs are inverted and automatically reverse the receiver's polarity. The polarity state is stored in the Reverse Polarity bit. If the Auto Polarity Disable bit is set, then the Reverse Polarity bit can be written to force the polarity reversal of the receiver. through hardware configuration. There is no support for Auto-Negotiation of the FX interface. Not all of the above combinations are possible due to limitations of the environment and the 802.3 standards. Legitimate operating states are: * * * * * * 10Base-T Half Duplex 10Base-T Full Duplex 100Base-TX Half Duplex 100Base-TX Full Duplex 100Base-FX Half Duplex (Port 3 only) 100Base-FX Full Duplex (Port 3 only)
INITIALIZATION AND SETUP
HARDWARE CONFIGURATION
Several different states of operation can be chosen through hardware configuration. External pins may be pulled either high or low at reset time. The combination of high and low values determines the power on state of the device. Many of these pins are multi-function pins which change their meaning when reset ends.
Only port 3 supports 100Base-FX. The Phy can be hardware configured to force any one of the above-mentioned modes. By forcing the mode, the Phy will only run in that mode, hence limiting the locations where the product will operate. The Phy is able to negotiate its mode of operation in the twisted pair environment using the AutoNegotiation mechanism defined in the clause 28 of IEEE 802.3u specification. ANeg can be enabled or disabled by hardware (ANEGA pin) or software (Reg. 0.12) control. When the ANeg is enabled, the Phy chooses its mode of operation by advertising its abilities and comparing them with the ability received from its link partner. It can be configured to advertise 100Base-TX or 10Base-T operating in either full or half duplex. Register 4 contains the current capabilities, speed and duplex, of the Phy, determined through hardware selects or chip defaults. The contents of Reg. 4 is sent to its link partner during the ANeg process using Fast Link Pulses (FLPs). An FLP is a string of 1s and 0s, each of which has a particular meaning, the total of which is called a Link Code Word. After reset, software can change any of these bits from 1 to 0 and back to 1, but not from 0 to 1. Therefore, the hardware has priority over software. When ANeg is enabled, the Phy sends out FLPs during the following conditions: * * * power on link loss restart ANeg command by software
SOFTWARE CONFIGURATION
Several different states of operation can be chosen through software configuration. Please refer to the SMI section as well as the Register Descriptions. LEDs Each of the 4 ports has 3 individual LED outputs available to indicate Speed, Duplex/Collision, and Link/Activity. These multi-function pins are inputs during reset and LED output pins thereafter. The level of these pins during reset determines their active output states. If a multi-function pin is pulled up during reset to select a particular function, then that LED output would become active low, and the LED circuit must be designed accordingly, and vice versa. (See LED Configuration.)
AUTO-NEGOTIATION
By definition the 10/100 Transceiver is able to run at either 10Mbps over Twisted Pair Copper (10Base-T), 100Mpbs over Twisted Pair Copper (100Base-TX) or 100Mpbs over Fiber Optics (100Base-FX). In addition the Phy is able to run in either half duplex (repeater mode) or full duplex. To determine the operational state, the Phy has hardware selects and software selects while also supporting AutoNegotiation and Parallel Detection. To run in 100Base-FX mode, the selection must be done
During this period, the Phy continually sends out FLPs while monitoring the incoming FLPs from the link partner to determine their optimal mode of operation. If FLPs are not detected during this phase of operation, Parallel Detection mode is entered (see below).
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
When the Phy receives 3 identical link code words (ignoring acknowledge bit) from its link partner, it stores these code words in Reg. 5, sets the acknowledge bit it the generated FLPs, and waits to receive 3 identical code word with the acknowledge bit set from the link partner. Once this occurs the Phy configures itself to the highest technology that is common to both ends. The technology priorities are: 1. 2. 3. 4. 100Base-TX, full-duplex 100Base-TX, half-duplex 10Base-T, full-duplex 10Base-T half-duplex. presented to the PCS in 5 bits symbol format. This loopback is used to check the operation of the 5-bit symbol decoder and the phase locked loop circuitry. In Local Loopback, the SD output is forced to logic one and TXOP/N outputs are tri-stated. In Remote Loopback, incoming data is passed through the equalizer and clock recovery, then looped back to the NRZI/MLT3 converter and then to the transmit driver. This loopback is used to ensure the device's connection on the media side. It also checks the operation of the device's internal adaptive equalizer, phase locked loop circuit, and wave-shaper synthesizer. During Remote Loopback, signal detect (SD) output is forced to logic zero. Cable Length Indicator The Phy can detect the approximate length of the cable it's attached and display the result in Reg. 20.[7:4]. A reading of [0000] translates to < 10m cable used, [0001] translates to ~ 10 meter of cable, and [1111] translates to 150 meter cable. The cable length value can be used by the network manage to determine the proper connectivity of the cable and to manage the cable plant distribution
Once the ANeg is complete, Reg. 1.5 is set, Reg. 1.[14:11] reflects negotiated speed and duplex mode, and the Phy enters the negotiated transmission and reception state. This state will not change until link is lost or the Phy is reset through either hardware or software, or the restart negotiation bit (Reg. 0.9) is set.
PARALLEL DETECTION
Because there are many devices in the field that do not support the ANeg process, but must still be communicated with, it is necessary to detect and link through the Parallel Detection process. The parallel detection circuit is enabled in the absence of FLPs. The circuit is able to detect: * * * Normal Link Pulse (NLP) 10Base-T receive data 100Base-TX idle
RESET AND POWER
The Phy can be reset in three ways: 1. 2. 3. During initial power on. Hardware Reset: A logic low signal of 150 s pulse width is applied to RST* pin. Software Reset: Write a one to SMI Reg. 0.15.
The mode of operation gets configured based on the technology of the incoming signal. If any of the above is detected, the device automatically configures to match the detected operating speed in the half duplex mode. This ability allows the device to communicate with the legacy 10Base-T and 100Base-TX systems, while maintaining the flexibility of Auto-Negotiation.
The power consumption of the device is significantly reduced due to its built-in power management features. Separate power supply lines are used to power the 10BaseT circuitry and the 100BaseTX circuitry. Therefore, the two circuits can be turnedon and turned-off independently. When the Phy is set to operate in 100Base-TX mode, the 10Base-T circuitry is powered down, and vice versa. The following power management features are supported: 1. Power down mode: This can be achieved by writing to Reg. 0.11 or pulling PWRDN pin high. During power down mode, the device is still be able to interface through the MDC/MDIO management interface. Energy detect / power saving mode: Energy detect mode turns off the power to select internal circuitry when there is no live network
DIAGNOSTICS
Loopback Operation Local Loopback and Remote Loopback are provided for testing purpose. They can be enabled by write to either Reg. 0.14 (LPBK) or Reg. 21.3 (EN_RPBK). The Local Loopback routes transmitted data through the transmit path back to the receiving path's clock and data recovery module. The loopback data are
2.
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
connected. Energy Detect (ED) circuit is always turned on to monitor if there is a signal energy present on the media. The SMI circuitry is also powered on and ready to respond to any management transaction. The transmit circuit still send out link pulses with minimum power consumption. If a valid signal is received from the media, the device will power up and resume normal transmit/receive operation. (Patent Pending) 3. Reduced Transmit Drive Strength mode: Additional power saving can be gained at the Phy level by designing with 1.25:1 turns ration magnetic and asserting the TP125 pin at reset.
CLOCK
The clock input must a TTL clock oscillator measured at 50 MHz-100PPM.
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver REGISTER DESCRIPTIONS
The first seven registers of the MII register set are defined by the MII specification. In addition to these required registers are several Altima Communications Inc. specific registers. There are reserved registers and/or bits that are for Altima internal use only. The following standard registers are supported. (Register numbers are in Decimal format, the values are in Hex format): NOTE: When writing to registers it is recommended that a read/modify/write operation be performed, as unintended bits may get set to unwanted states. This applies to all registers, including those with reserved bits.
REGISTERS 1-7
Register 0 1 2 3 4 5 6 7 Description Control Register Status Register PHY Identifier 1 Register PHY Identifier 2 Register Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Next Page Advertisement Register Default 3000 7849 0022 5541 01E1 0001 0004 2001
REGISTERS 8-31
Register 8-15 16 17 18 19 20 21 22 23 24 25-31 Description Reserved Polarity and Interrupt Level Register Interrupt Control/Status Register Diagnostic Register Power/Loopback Register Cable Measurement Register Receive Error Counter Register Reserved Reserved Mode Control Register Reserved Default XXXX 03C0 0000 5020 8060 XXXX 0304 XXXX 0000 0000 XXXX
LEGEND: RW SC LL RO RC LH Read and Write Access Self Clearing Latch Low until cleared by reading Read Only Cleared on Read Latch High until Cleared by reading
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
Register 0: Control Register Reg.bit 0.15 0.14 Name Reset Loopback Description 1 = PHY reset. This bit is self-clearing. 1 = Enable loopback mode. This will loopback TXD to RXD and ignore all the activity on the cable media. 0 = Normal operation. 1 = 100Mbps 0 = 10Mbps. 1 = Enable Auto-Negotiate process (overrides 0.13 and 0.8) 0 = Disable Auto-Negotiate process. Mode selection is controlled via bit 0.8, 0.13 or through mode pin. 1 = Power down. All blocks except for SMI will be turned off. Setting PWRDN pin to high will achieve the same result. 0 = Normal operation. 1 = N/A 0 = Normal operation. 1 = Restart Auto-Negotiation process. 0 = Normal operation. 1 = Full duplex. 0 = Half duplex. 1 = Enable collision test, which issues the COL signal in response to the assertion of TX_EN signal. Collision test is disabled if PCSBP pin is high. Collision test is enabled regardless of the duplex mode. 0 = Disable COL test. * Refer to Mode Table Mode RW/SC RW Default 0 0
0.13 0.12
Speed Select ANeg Enable
RW RW
* See Note * See Note
0.11
Power Down
RW
0
0.10 0.9 0.8
Isolate Restart ANeg Duplex Mode
R RW/SC RW
0 0 * See Note
0.7
Collision Test
RW
0
0.[6:0]
Reserved
RW
0000000
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
Register 1: Status Register Reg.bit 1.15 1.14 1.13 1.12 1.11 1.[10:7] 1.6 Name 100Base-T4 100Base-TX Full Duplex 100Base-TX Half Duplex 10Base-T Full Duplex 10Base-T Half Duplex Reserved MF Preamble Suppression ANeg Complete Description Permanently tied to zero indicates no 100BaseT4 capability. 1 = 100BaseTX full duplex capable. 0 = Not 100BaseTX full duplex capable. 1 = 100BaseTX half duplex capable. 0 = Not TX half-duplex capable. 1 = 10BaseT full duplex capable. 0 = Not 10BaseT full duplex capable. 1 = 10BaseT half duplex capable. 0 = Not 10BaseT half duplex capable. The Phy is able to perform management transaction without MDIO preamble. The management interface needs minimum of 32 bits of preamble after reset. 1 = Auto-Negotiate process completed. Reg. 4, 5, 6 are valid after this bit is set. 0 = Auto-negotiate process not completed. 1 = Remote fault condition detected. 0 = No remote fault. This bit will remain set until it is cleared by reading register 1. 1 = Able to perform Auto-Negotiation function, default value determined by ANEGA pin. 0 = Unable to perform Auto-Negotiation function. 1 = Link is established. If link fails, this bit will be cleared and remain at 0 until register is read again. 0 = Link has gone down. 1 = Jabber condition detect. 0 = No Jabber condition detected. 1 = Extended register capable. This bit is tied permanently to one. * Refer to Mode Table Mode RO RO RO RO RO RO RO Default 0 * See Note * See Note * See Note * See Note 0000 1
1.5
RO
0
1.4
Remote Fault
RO/LH
0
1.3
ANeg Ability
RO
ANEGA
1.2
Link Status
RO/LL
0
1.1 1.0
Jabber Detect Extended Capability
RO/LH RO
0 1
Register 2: PHY Identifier 1 Register Reg.bit 2.[15:0] Name OUI* Description Composed of the 3rd through 18th bits of the Organizationally Unique Identifier (OUI), respectively. * = Based on an OUI is 0010A9 (Hex) Mode RO Default 0022(H)
Register 3: PHY Identifier 2 Register Reg.bit 3.[15:10] 3.[9:4] 3.[3:0] Name OUI Model Number Revision Number Description Assigned to the 19th through 24th bits of the OUI. Six bit manufacturer's model number. 101 is encoded as 010001. Four-bit manufacturer's revision number. 0001 stands for Rev. B, etc. * = Based on an OUI of 0010A9 (Hex) Mode RO RO RO Default 010101 010100 0001
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
Register 4: Auto-Negotiation Advertisement Register Reg.bit 4.15 4.14 4.13 4.[12:11] 4.10 Name Next Page Acknowledge Remote Fault Reserved FDFC Description 1 = Next Page enabled. 0 = Next Page disabled. This bit will be set internally after receiving 3 consecutive and consistent FLP bursts. 1 = Advertises that this device has detected a Remote Fault. 0 = No remote fault detected. For future technology. Full Duplex Flow Control 1= Advertise that the DTE(MAC) has implemented both the optional MAC control sublayer and the pause function as specified in clause 31 and annex 31B of 802.3u. 0= MAC does not support flow control Technology not supported. This bit always 0 1 = 100BaseTX full duplex capable. 0 = Not 100BaseTX full duplex capable. 1 = 100BaseTX half duplex capable. 0 = Not TX half duplex capable. 1 = 10BaseT full duplex capable. 0 = Not 10BaseT full duplex capable. 1 = 10BaseT half duplex capable. 0 = Not 10BaseT half duplex capable. Protocol Selection [00001] = IEEE 802.3. * refer to Mode Table Mode RW RO RW RW Default 0 0 0 000
4.9 4.8 4.7 4.6 4.5 4.[4:0]
100Base-T4 100Base-TX Full Duplex 100Base-TX 10Base-T Full Duplex 10Base-T Selector Field
RO RW RW RW RW RO
0 * See Note * See Note * See Note * See Note 00001
Register 5: Auto-Negotiation Link Partner Ability Register/Link Partner Next Page Message Reg.bit 5.15 5.14 5.13 5.[12:10] 5.9 5.8 5.7 5.6 5.5 5.[4:0] Name Next Page Acknowledg e Remote Fault Reserved 100Base-T4 100Base-TX Full Duplex 100Base-TX 10Base-T Full Duplex 10Base-T Description 1 = Link partner desires Next Page transfer. 0 = Link partner does not desire Next Page transfer. 1 = Link Partner acknowledges reception of FLP words. 0 = Not acknowledged by Link Partner. 1 = Remote Fault indicated by Link Partner. 0 = No remote fault indicated by Link Partner. For future technology. 1 = 100BaseT4 supported by Link Partner. 0 = 100BaseT4 not supported by Link Partner. 1 = 100BaseTX full duplex supported by Link Partner. 0 = 100BaseTX full duplex not supported by Link Partner. 1 = 100BaseTX half duplex supported by Link Partner. 0 = 100BaseTX half duplex not supported by Link Partner. 1 = 10Mbps full duplex supported by Link Partner. 0 = 10Mbps full duplex not supported by Link Partner. 1 = 10Mbps half duplex supported by Link Partner. 0 = 10Mbps half duplex not supported by Link Partner. Protocol Selection [00001] = IEEE 802.3. Mode RO RO RO RO RO RO RO RO RO Default 0 0 0 000 0 0 0 0 0 00001
Selector RO Field *When this register is used as Next Page Message, the bit definition is the same as Register 7.
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
Register 6: Auto-Negotiation Expansion Register Reg.bit 6.[15:5] 6.4 Name Reserved Parallel Detection Fault Description 1 = Fault detected by parallel detection logic, this fault is due to more than one technology detecting concurrent link up condition. This bit can only be cleared by reading Register 6 using the management interface. 0 = No fault detected by parallel detection logic. 1 = Link partner supports next page function. 0 = Link partner does not support next page function. Next page is supported. This bit is set when a new link code word has been received into the Auto-Negotiation Link Partner Ability Register. This bit is cleared upon a read of this register. 1 = Link partner is Auto-Negotiation capable. 0 = Link partner is not Auto-Negotiation capable. Mode RO RO/LH Default 0 0
6.3 6.2 6.1
Link Partner Next Page Able Next Page Able Page Received
RO RO RC
0 1 0
6.0
Link Partner ANeg-Able
RO
0
Register 7: Auto-Negotiation Next Page Transmit Register Reg.bit 7.15 7.14 7.13 7.12 7.11 17.[10:0] Name NP Reserved MP ACK2 TOG_TX CODE Description 1 = Another Next Page desired. 0 = No other Next Page Transfer desired. 1 = Message page. 0 = Un-formatted page. 1 = Will comply with message. 0 = Cannot comply with message. 1 = Previous value of transmitted link code word equals to 0. 0 = Previous value of transmitted link code word equals to 1. Message/Un -formatted Code Field. Mode RW RO RW RW RW RW Default 0 0 1 0 0 001
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
Register 16: BT and Interrupt Level Control Register Reg.bit 16.15 16.14 16.13 16.12 16.11 Name Reserved INTR_LEVL TXJAM Reserved SQE Test Inhibit Description 1=INTR pin will be active high. 0=INTR pin will be active low. 1 = Force CIM to send JAM pattern 0 = Normal operation 1 = Disable 10BaseT SQE testing. 0 = Enable 10BaseT SQE testing, which will generate a COL pulse following the completion of a packet transmission. 1 = Disable Auto Polarity detection/correction. 0 = Enable Auto Polarity detection/correction. 1= Reverse Polarity when Reg. 16.5 = 0 0= Normal Polarity when Reg. 16.5 = 0 If Reg. 16.5 is set to 1, writing a one to this bit will reverse the polarity of the transmitter. Mode RW RW RW RO RW Default 0 0 0 0 0
16.[10:6] 16.5 16.4
Reserved Auto Polarity Disable Reverse Polarity
RO RW RW
0 0 0
16.[3:0]
Reserved
RO
0
Register 17: Interrupt Control/Status Register Reg.bit 17.15 17.14 17.13 17.12 17.11 17.10 17.9 17.8 17.7 17.6 17.5 17.4 17.3 17.2 17.1 17.0 Name Jabber_IE Rx_Er_IE Page_Rx_IE PD_Fault_IE LP_Ack_IE Link_Not_OK_IE R_Fault_IE ANeg_Comp_IE Jabber_Int Rx_Er_Int Page_Rx_Int PD_Fault_Int LP_Ack_Int Link_Not_OK Int R_Fault_Int ANeg _Comp Int Description Jabber Interrupt Enable. Receive Error Interrupt Enable. Page Received Interrupt Enable. Parallel Detection Fault Interrupt Enable. Link Partner Acknowledge Interrupt Enable. Link Status Not OK Interrupt Enable. Remote Fault Interrupt Enable. Auto-Negotiation Complete Interrupt Enable. This bit is set when a jabber event is detected. This bit is set when RX_ER transitions high. This bit is set when a new page is received during ANeg. This bit is set when parallel detect fault is detected. This bit is set when the FLP with acknowledge bit set is received. This bit is set when link status switches from OK status to Non-OK status (Fail or Ready). This bit is set when remote fault is detected. This bit is set when ANeg is complete. Mode RW RW RW RW RW RW RW RW RC RC RC RC RC RC RC RC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
Register 18: Diagnostic Register Reg.bit 18.[15:12] 18.11 18.10 18.9 Name Reserved DPLX Speed RX_PASS Description The result of Auto-negotiation: Full-duplex =1; Half-duplex = 0 The result of Auto-neg. for speed: 100base-TX = 1; 10Base-T = 0. In 10BT mode, this bit indicates that Manchester data has been detected. In 100BT mode, it indicates valid signal has been received but not necessarily locked on to. Indicates the receive PLL has locked onto the received signal for the selected speed of operation (10Base-T or 100Base-TX). This bit is set whenever a cycle-slip occurs, and will remain set until it is read. Mode RO RO RO RO Default 0 0 0 0
18.8
RX_LOCK
RO/RC
0
18.[7:0]
Reserved
RO
0
Register 19: Power/Loopback Register Reg.bit 19.[14:7] 19.6 Name Reserved TP125 Description Reserved Transmit transformer ratio selection. 1 = 1.25:1 0 = 1:1 The default value of this bit is controlled by TP125 pin. 1 = Enable advanced power saving mode. 0 = Disable advanced power saving mode. Reserved 1 = In ANeg test mode, send NLP instead of FLP in order to test NLP receive integrity. 0 = Sending FLP in ANeg test mode. Reserved Mode RW RW Default 00 0
19.5 19.[4:2] 19.1
Low Power Mode Reserved NLP Link Integrity Test Reserved
RW RW RW
1 00 0
19.0
RW
0
Register 20: Cable measurement capability Register Reg.bit 20.[15:8] 20.[7:4] Name Reserved Cable measurement capability Description These bits can be used as cable length indicator. The bits are incremented from 0000 to 1111, with an increment of approximately 10 meters. The equivalent is 0 to 32 dB with an increment of 2 dB @ 100 MHz. The value is a read back from the equalizer, and the measured value is not absolute. Mode RO RO Default 0 0
20.[3:0]
Reserved
RO
0
Register 21: Receive Error Counter Reg.bit 21.[15:0] Name RX_ER Counter Description Count Receive Error Events Mode RO Default 0
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
Register 24: Mode Control Register Reg.bit 24.15 Name SDCM_Sel Description Select Common Mode Voltage for FX Signal Detect. 1 = Select internal common mode setting. 0 = Select external common mode setting. 1 = Force 10B-T link up without checking NLP. 0 = Normal Operation. 1 = Ignore link in 100Base-TX and transmit data. ANeg must be disabled at this time (ANEGA pin tied low). 0 = Normal Operation. 1 = Disable Jabber function in PHY. 0 = Enable Jabber function in PHY. 1 = Activity LED only responds to receive operation. 0 = Activity LED responds to receive and transmit. This bit should be ignored when Reg. 0.8 is set one. 1 = Disable Far End Fault Insertion. 0 = Enable Far End Fault Insertion and detection function. This bit valid when FX mode is enabled. 1 = Force transmission of Far End Fault Insertion pattern. 0 = Normal operation. 1 = Receive Error Counter full. 0 = Receive Error Counter not full. 1 = Disable Receive Error Counter. 0 = Enable Receive Error Counter. 1 = Disable the watchdog timer in the decipher. 0 = Enable watchdog timer. 1 = Enable remote loopback. 0 = Disable remote loopback. 1 = Enable 100M data scrambling. 0 = Disable 100M data scrambling. When FX mode is selected, this bit will be forced to zero. 1 = FX mode selected. 0 = Disable FX mode. Mode RO Default 0
24.14 24.13
NLP Disable Force_link_up
RW RW
0 0
24.12 24.11 24.10
Jabber Disable Reserved Conf_ALED
RW RO RW
0 0 0
24.9 24.8
Reserved FEF_Disable
RO RW
0 Set by FORCE 100
24.7
Force FEF Transmit Rx_Er_Cnt Full Disable Rx_Er_Cnt Dis_WDT En_RPBK Dis_Scrm
RW
0
24.6 24.5 24.4 24.3 24.2
RO/ RC RW RW RW RW
0 0 0 0 Set by SCRAM_EN
24.1 24.0
Reserved FX_SEL
RO RW
0 Set by !FX_DIS
Mode Table FX_Dis 0 1 1 1 1 Force 100 X X 1 0 1 Scram_En 1 1 1 1 0 ANEGA 1 1 0 0 0 Condition Port 3 100Base-FX Port 0-2 Auto Negotiate 10Base-T or 100Base-TX Port 0-3 Auto Negotiate 10Base-T or 100Base-TX Port 0-3 Forced to 100Base-TX Port 0-3 Forced to 10Base-T Port 0-3 Forced to 100Base-TX (unscrambled)
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver 4B/5B CODE-GROUP TABLE
PCS Code Group[4:0] 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 SYMBOL Name 0 1 2 3 4 5 6 7 8 9 A B C D E F I J K T R MII (TXD/RXD [3:0]) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Idle and Control Code 0000 0101 0101 Undefined Undefined Invalid Code 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 H V V V V V V V V V V Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Transmit Error; used to send HALT codegroup Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Inter-Packet Idle; used as inter-stream fill code. Start of stream delimiter, part 1 of 2; always use in pair with K symbol. Start of stream delimiter, part 2 of 2; always use in pair with J symbol. End of stream delimiter, part 1 of 2; always use in pair with R symbol. End of stream delimiter, part 2 of 2; always use in pair with T symbol. Description Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data A Data B Data C Data D Data E Data F
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver SMI READ/WRITE SEQUENCE
SMI Read/Write Sequence Pream (32 bits) 1...1 1...1 Start (2 bits) 01 01 OpCode (2 bits) 10 01 PHYAD (5 bits) AAAAA AAAAA REGAD (5 bits) RRRRR RRRRR TurnAround (2 bits) Z0 10 Data (16 bits) D...D D...D Idle Z Z
Read Write
LED CONFIGURATIONS
Mode 10M Link 10M HDX Transmit 10M HDX Receive 10 HDX Collision 10M FDX Transmit 10M FDX Receive 100M Link 100M HDX Transmit 100M HDX Receive 100 HDX Collision 100M FDX Transmit 100M FDX Receive LEDDPX OFF OFF ON during collision ON ON OFF OFF ON during collision ON ON LEDACT ON TOGGLE TOGGLE TOGGLE TOGGLE TOGGLE ON TOGGLE TOGGLE TOGGLE TOGGLE TOGGLE LEDSPD OFF OFF OFF OFF OFF OFF ON ON ON ON ON ON
Vcc
300 10K Multi Function LED pin pulled high for reset. Multi Function LED pin pulled low for reset. 10K 300
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver ELECTRICAL CHARACTERISTICS
NOTE: The following electrical characteristics are design goals rather than characterized numbers.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature............................... -55o C to +150o C Vcc Supply Referenced to GND............. -0.5V to +5.0V Digital Input Voltage............................... -0.5V to Vcc DC Output Voltage.................................. -0.5V to Vcc
OPERATING RANGE
Operating Temperature(Ta) ........................... -40o C to +85o C Vcc Supply Voltage Range(Vc c) .................. 2.97V to 3.63V
Total Power Consumption Parameter Supply Current (per port) Symbol Icc Conditions 10 Base-T, Idle 10 Base-T, Normal activity 100 Base-TX 100 Base-FX 10/100 Base-TX, low power without cable Power down Min Typ 25 41 85 30 12 Max 30 75 100 40 15 1 Units mA mA mA mA mA mA
TTL I/O Characteristics Parameter Input Voltage High Input Voltage Low Input Current Output Voltage High Output Voltage Low Output Current High Output Current Low Input Capacitance Output Transition Time Tristate Leakage Current REFCLK and XTAL Pins Parameter Input Voltage Low Input Voltage High Input Clock Frequency Tolerance Input Clock Duty Cycle Input Capacitance Symbol Vil Vih F Tdc Cin Conditions Min 2.0 40 3.0 50 60 Typ Max 0.8 Units V V ppm % pF Symbol Vih Vil Ii Voh Vol Ioh Iol Ci 3.15V < VCC < 3.45V |Ioz| Conditions Min 2.0 -10 VCC-0.4 0.8 10 0.4 8 -8 10 5 10 Typ Max Units V V mA V V mA mA pF ns uA
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
I/O Characteristics - LED/CFG Pins Parameter Output Low Voltage Output High Voltage Input Current Output Current Symbol Vol Voh Ii Io Conditions Min 2.4 -8 -10 Typ Max 0.4 8 10 Units V V mA mA
100 BASE-TX Transceiver Characteristics Parameter Peak to Peak Differential Output Voltage Output Voltage Symmetry Signal Rise/Fall Time Rise/Fall Time Symmetry Duty Cycle Distortion Overshoot/Undershoot Output Jitter Receive Jitter Tolerance Output Current High Output Current High Common Mode Input Voltage Common Mode Input Current Differential Input Resistance Symbol Vp Vss Trf Trfs Dcd Vos Conditions Note 1 Note 1 Note 1 Note 1 Min 1.9 .98 3.0 3 Typ 2.0 Max 2.1 1.02 5.0 4 250 5 1.4 4 40 32 10 5 Note 1: 50 ( 1%) resistor to VCC on each output 10 BASE-T Transceiver Characteristics Parameter Peak to Peak Differential Output Voltage Signal Rise/Fall Time Output Current Sink Output Current High Output Current High Start of Idle Pulse Width Output Jitter Receive Jitter Tolerance Receive Input Impedance Differential Squelch Threshold Common Mode Rejection Differential Input Resistance Symbol Vop Conditions Note 1 Min 4.5 1 15 Ioh Ioh 1:1 Transformer 1.25:1 Transformer 300 Typ 5 Max 5.5 4 16 100 80 350 1.4 32 500 Units V ns mA mA mA ns ns ns K mV V K Units V mV ns ns ps % ns ns mA mA V uA K
4
Scrambled Idle Ioh Ioh 1:1 Transformer 1.25:1 Transformer 1.8
Zin Vds
3.6 300
400 25
25 Note 1: 50 ( 1%) resistor to VCC on each output
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
100 BASE-FX Transceiver Characteristics Parameter Differential Output Voltage High Differential Output Voltage Low Signal Rise/Fall Time Output Jitter Differential Output Voltage High Differential Output Voltage Low Common-Mode Input Voltage Input Differential Output Current Sink Symbol Voh Vol Conditions Note 1 Note 1 Min 2.2 1.4 1 2.1 1.5 1.3 150 15 Note 1: 69 to 3.3V VCC and 183 to ground 10 BASE-T Link Integrity Timing Characteristics Parameter Time Link Loss Receiver Link Pulse Link Min Receive Timer Link Max Receive Timer Link Transmit Period Link Pulse Width Symbol Conditions Min 50 2 2 50 8 60 Typ Max 150 7 7 150 24 150 Units ms Link Pulses ms ms ms ns Typ Max 2.5 1.7 4 1.4 2.4 1.8 3.1 16 Units V V ns ns V V V mV mA
Vih Vil
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
DIGITAL TIMING CHARACTERISTICS
Power on Reset Parameter RST* Low Period Configuration SYM tRST tCONF Conditions Min 150 100 Typ Max Units s ns
tRST
RST* All Configuration Pins Power on Reset Timing
tCONF
Management Data Interface Parameter Mgt CLOCK Mgt CLOCK MDIO Setup MDIO Hold SYM tMDCL tMDCH tMS tMH Conditions Min 20 20 10 10 Typ Max Units ns ns ns ns
Setup on Read/Write Cycle Hold on Read/Write Cycle
tMDCL
MDC
tMDCH
tMS
MDIO
tMH
Management Data Interface Timing
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
100Base -TX/FX & 10Base -T RMII Transmit System Timing Parameter REFCLK period REFCLK High period REFCLK Low period TX_EN to /J/ (SOP) !TX_EN to /T/ (EOP) TX Propagation Delay TXD[1:0], TX_EN Setup TXD[1:0], TX_EN Hold !TX_EN to TX_EN SYM tCK tCKH tCKL tTJ tTT tTJ tTXS tTXH tTX_TX Conditions Min 19.999 9.000 9.000 60 60 60 4 0 120 End of Packet Typ 20.000 10.000 10.000 Max 20.001 11.000 11.000 100 100 100 2 Units ns ns ns ns ns ns ns ns ns
From TXD[1:0] to TXOP/N(_FX) From rising edge of REFCLK From rising edge of REFCLK
tCK tCKH
REFCLK
Start of Packet tCKL
tTXS
TX_EN
tTX_TX tTXH
TXD[1:0]
tTJ
TXOP/N
/J/
tTT
/T/
FXTP/N
TXOP/N 100Base-TX/FX & 10Base -T RMII Transmit Timing
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
100Base -TX/FX & 10Base -T RMII Receive System Timing Parameter REFCLK period REFCLK High period REFCLK Low period /J/K (SOP) to CRS_DV /T/R (EOP) to !CRS_DV RX Propagation Delay RXD[1:0], CRS_DV, RX_ER Setup RXD[1:0], CRS_DV, RX_ER Hold SYM tCK tCKH tCKL tRCSA tRCSD tRDVA tRXS tRXH Conditions Min 19.999 9.000 9.000 80 120 4 5 Typ 20.000 10.000 10.000 40 Max 20.001 11.000 11.000 150 190 180 Units ns ns ns ns ns ns ns ns
From RXIP/N(_FX) to RXD[1:0] From rising edge of REFCLK From rising edge of REFCLK
tCK tCKH
REFCLK
Start of Packet tCKL
End of Packet
tRDVA
CRS_DV
tRDVD tRXS tRXH
RXD[1:0] RX_ER /J/K RXIP/N /T/R
FXRP/N SOP RXIP/N 100Base-TX/FX & 10Base-T RMII Receive Timing EOP
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
TX APPLICATION TERMINATION
Please contact Altima Communications Inc. for the latest component value recommendation
3.3V
49.9 1%
49.9 1%
0.1 F
AC104QF Transformer TXON TXOP TXC_P TX+_P TX-_P RX+_P RX-_P RXC_P
10 K 1% 0.1 F
RJ45 1 TX+ 2 TX3 RX+ 4 Unused 5 Unused 6 RX7 Unused 8 Unused
TXC_S TX+_S TX-_S RX+_S RX-_S RXC_S
IBREF
75 X 4
RXIP
110 1%
RXIN
1000 pF 3 KV
Chassis GND
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AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
FX APPLICATION TERMINATION
Please contact Altima Communications Inc. for the latest component value recommendation To enable the FX mode, FX_DIS pin must be pulled low by a 1 K resistor.
3.3V 1.3 K 69.8 69.8 130 1 uHL 1 uHL 0.1 uF
0.1 uF
AC104-QF
10 uF
HFBR-5903 1 RXVee 2 RXVcc 3 SD 4 RD5 RD+ 6 TXVcc 7 TXVee 8 NC 9 TD+ 10 TD-
SDP SDN FXRN
100
FXRP FXTP
182
130
130
2K
1K
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82
FX_DIS
182
0.1 uF
FXTN
AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
POWER AND GROUND FILTERING FOR AC104QF
Please contact Altima Communications Inc. for the latest component value recommendation. Ground Power .1uf Cap Components placed < 3mm from pin
80
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98 99 100 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31
96
87
83
77
73 72
AC104QF
44 49
62 59
54 52
AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
PACKAGE DIMENSIONS FOR AC104QF (100 PIN PQFP)
Quad Flat Pack Outline (20 x 14 mm)
N 100
A 3.40 Max
A1 0.25 Min
A2 2.70 0.2
B 0.3 0.1
D 23.20 0.25
D1 20.00 0.10
E 17.20 0.25
E1 14.00 0.10
e 0.65
L 0.88 0.2
L1 1.60 0.12
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